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MITSUBISHI
M66273FP
Ver.3.1 Dec,1999
LCD CONTROLLER with VRAM
* Displayable LCD * Binary display Monochrome STN-LCD of up to 153600 dots(equivalent to 1/2 VGA) * 4 gray scale display Monochrome STN-LCD of up to 76800 dots(equivalent to 1/4 VGA) Reflective color STN-LCD of up to 76800 dots (equivalent to 1/4 VGA) * Interface with MPU * Capability of switching the interface with two-way 8/16-bit MPU * Provides WAIT output pin(WAIT output when access from MPU to VRAM is gained) * Capability of controlling BHE or LWR/HWR at the interface with a 16-bit MPU * Interface with LCD * LCD display data bus is a 4-bit or 8-bit parallel output. * 4 kinds of control signals: CP, LP, FLM and M * Display functions * Graphic display only * Binary or 4 gray scale display(gray scale palette is used to set pseudo medium 2 gray scale.) * Reflective color(ECB) uses a gray scale function. * Vertical scrolling is allowed within memory range. * Additional function for LCD module built-in system * Capability of interfacing with two-way 8/16-bit MPU(16-bit MPU byte access is not allowed.) * Access from MPU to VRAM is gained via the I/O register. * 5V or 3V single power supply
DESCRIPTION
The M66273 is a graphic display-only controller for dot matrix type STNLCD which is used widely for OA equipment, PDA, amusement equipment, etc. The M66273 is an advanced product from the M66272 at the point of MPU interface and timing specifications. This LCD display functions are the same with the M66272. It is capable of displaying six types of LCD by combining the panel configuration(single or dual scan), LCD display function(binary or gray scale), LCD display data bus width(4 or 8 bit).
Binary/ Panel Displayable LCD size configuration gray scale LCD display data 4bit Binary Equivalent to 640 x 240 8bit Single scan 4bit Gray scale Equivalent to 320 x 240 8bit 4bit Binary Equivalent to 320 x 240 x 2 screens Dual scan Equivalent to 320 x 120 x 2 screens Gray scale 4bit
The M66273 can support the reflective color type LCD (ECB : Electrically Controlled Birefringence). The IC has a built-in 19200-byte VRAM as a display data memory. All of the VRAM addresses are externally opened. Direct addressing of display data can be performed from MPU, thus display data processing such as drawing can be efficiently carried out. The built-in arbiter circuit(cycle steal system) which gives priority to display access allows timing-free access from MPU to VRAM, preventing display screen distortion. The IC provides has a function for LCD module built-in system by lessening connect pins between the MPU and the IC.
APPLICATION
PPC/FAX operation panel, display/operation panel of other OA equipment, multifunction/public telephone * PDA/electronic notebook/information terminal, portable terminal * Game, Amusements, Kids computer, etc.
FEATURES
* Display memory *Built-in 19200-byte(153.6-Kbit) VRAM(Equivalent to 640 x 240 dots x 1 screen, 320 x 240 dots x 2 screens) * All addresses of built-in VRAM are externally opened.
PIN CONFIGURATION (TOP VIEW)
VSS CP DISPLAY DATA LATCH PULSE LP DISPLAY DATA TRANSFER CLOCK
65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80
40 39 38 37 36 35 34
FIRST LINE MARKER SIGNAL FLM
VD<0> VD<1> VD<2> VD<3> VD<4> VD<5> VD<6> VD<7> VDD N.C N.C VSS
LCD DISPLAY DATA BUS
M66273FP
33 32 31 30 29 28 27 26 25
VSS N.C N.C N.C CYCLE STEAL CSE ENABLE VSS VDD WAITCNT WAIT CONTROL A<14> A<13> A<12> A<11> A<10> A<9> A<8> VSS
MPU ADDRESS BUS
Outline 80P6N-A
N.C : No Connection
1
MITSUBISHI
M66273FP
Ver.3.1 Dec,1999
LCD CONTROLLER with VRAM
BLOCK DIAGRAM 1
15
VDD
8 23 34 42 52 63 77
MPU ADDRESS BUS
A<14:0>
22 26 32
ADDRESS BUFFER CONTROL REGISTER LCD DISPLAY TIMING CONTROL CIRCUIT
43
LCD CONTROL SIGNAL DISPLAY DATA 66 CP TRANSFER CLOCK DISPLAY DATA 67 LP LATCH PULSE FLM FIRST LINE MARKER 68 SIGNAL LCD ALTERNATING 62 M SIGNAL
61 LCDENB
MPU DATA BUS
D<15:0>
50 53 60
DATA BUFFER
VRAM
CONTROLREGISTER IOCS CHIP SELECT VRAM CHIP SELECT MCS HIGH WRITE STROBE HWR LOW WRITE STROBE LWR
2 6 3 4 5 12 11 14 33 9 7 36
19200byte
LCD DISPLAY DATA CONTROL CIRCUIT
69
VD<7:0> LCD DISPLAY
76
DATA BUS
RD READ STROBE 8/16MPU SELECT MPUSEL
RESET
RESET
MPU I/F CONTROL CIRCUIT
BHE BUS HIGH ENABLE WAIT CONTROL WAITCNT MPU CLOCK MPUCLK WAIT WAIT CYCLE STEAL ENABLE CSE
BUS ARBITER TIMING CONTROL CLOCK CONTROL (BASIC TIMING CONTROL) (CYCLE STEAL CONTROL)
1 10 13 24 25 35 40 41 51 64 65 80
37 38 39 78 79
VSS
N.C
BLOCK DIAGRAM 2 (When interfacing with the LCD module built-in system and having the maximum number of pins connected with MPU)
INPUT FIXED PIN
3 6 11 12 14 15 26 32 33
OPEN PIN
7 36
VDD
8 23 34 42 52 63 77
16
MPU ADDRESS BUS
A<7:1>
22
ADDRESS BUFFER CONTROL REGISTER LCD DISPLAY TIMING CONTROL CIRCUIT
43
MPU DATA BUS
D<15:0>
50 53 60
DATA BUFFER
VRAM ADDRESS INDEX REGISTER DATA PORT REGISTER
LCD CONTROL SIGNAL DISPLAY DATA 66 CP TRANSFER CLOCK DISPLAY DATA 67 LP LATCH PULSE FIRST LINE MARKER 68 FLM SIGNAL LCD ALTERNATING 62 M SIGNAL
61 LCDENB
VRAM 19200byte
LCD DISPLAY DATA CONTROL CIRCUIT
69
CONTROL REGISTER CHIP SELECT
IOCS
2
VD<7:0> LCD DISPLAY
DATA BUS
76
LOW WRITE STROBE READ STROBE
LWR RD
4 5
MPU I/F CONTROL CIRCUIT
BUS ARBITER TIMING CONTROL CLOCK CONTROL (BASIC TIMING CONTROL)
1 10 13 24 25 35 40 41 51 64 65 80 37 38 39 78 79
MPU CLOCK
MPUCLK
9
VSS 2
N.C
MITSUBISHI
M66273FP
Ver.3.1 Dec,1999
LCD CONTROLLER with VRAM
PIN DESCRIPTIONS
Item Pin name Output D<15:0>
Input/
Function
Number of pins
MPU data bus Input/ Output When selecting 8 bit MPU by MPUSEL input, connect D<15:8> to "VDD" or "VSS". MPU address bus When selecting 8-bit MPU, use A<14:0>. When selecting 16-bit MPU, use A<14:1> as a address bus. By combining A<0> and BHE, access to internal VRAM can be gained. When driving two screens (dual scan mode), notice that the allowable setup range of VRAM address is restricted. When IOCS control use A <7:0>, and MCS control use A <14:0> for selecting address of control register. Chip select input of control register When this pin is "L", select the internal control register. Assign to I/O space of MPU.
Chip select input of VRAM / control register When this pin is "L", select the internal VRAM. Assign to memory space of MPU. And this pin can for chip select of control register. In detail, refer to "COMBINATIONS OF CONTROL INPUT PINS ON THE MPU INTERFACE" and "CONTROL REGISTER".
16
A<14:0>
Input
15
IOCS
Input
1 1
MCS
Input
HWR
Input Input Input Input
LWR RD MPU interface MPUSEL
High-Write strobe input When this pin is "L", write data to the internal VRAM. HWR is valid only in using 16-bit MPU controlled byte access by LWR and HWR. Low-Write strobe input When this pin is "L", write data to the internal control register or VRAM. Read strobe input When this pin is "L", read data from the internal control register or VRAM. 8/16-bit MPU select input According to MPU, set "VSS" for 8-bit MPU and set "VDD" for 16-bit MPU. Reset input Use reset signal of MPU. When this pin is "L", initialize (reset) all internal control registers and counters. MPU clock Input system clock output from MPU. Bus-High-Enable input This pin is valid when using 16-bit MPU controlling byte access with A<0> and BHE. Connect to "VDD" to select 8-bit MPU.
Wait control input This pin is used for controlling WAIT output timing when requested access from MPU to VRAM. Use this pin, when it is necessary to output WAIT earlier than the timing of falling edge of overlapping with MCS and RD or LWR and HWR. And then connect AS, ALE or etc of MPU. Connect WAITCNT to "VDD" or "VSS", when it is necessary to output WAIT at the timing of falling edge of overlapping with MCS and RD or LWR and HWR.
1 1 1 1
RESET MPUCLK
Input Input
1 1
BHE
Input
1
WAITCNT Input
1
WAIT
Output
CSE
Output
WAIT output for MPU This signal makes WAIT for MPU. In case of fixed WAITCNT input("VSS" or "VDD" )change WAIT to "L" at the timing of falling edge of overlapping with MCS and RD or LWR and HWR. And in case of using WAITCNT input, change WAIT to "L" at timing of falling edge of WAITCNT on MCS = "L". And WAIT output return to "H" at synchronization with the rising edge of MPUCLK after internal processing. (Output WAIT only when requested access from MPU to VRAM is gained during cycle steal access.) Cycle Steal Enable output State output of internal cycle steal access.
1
1
3
MITSUBISHI
M66273FP
Ver.3.1 Dec,1999
LCD CONTROLLER with VRAM
PIN DESCRIPTIONS
Item Pin name
Input/ Output
Function Display data bus for LCD Transfer the LCD display data in synchronization with a rising edge of CP by putting 4-bit or 8-bit in parallel. The VD output pin in use differs depending on the number of driven screens and the display mode. Display data transfer clock Shift clock for the transfer of display data to LCD. Take the display data of VD to LCD at falling edge of CP. Display data latch pulse This clock use both as the latch pulse of display data for LCD and the transfer of scanning signal. LP is output when it finishes transferring display data of a line. Latch of display data and the transfer of scanning signal at falling edge of LP. First Line Marker signal output Output the start pulse of scanning line. This signal is "H" active, the IC for driving scanning line catches FLM at falling edge of LP. LCD alternating signal output Signal for driving LCD by alternating current. LCD (ON/OFF) control signal output Output data which is set at bit "0" of mode register (R1) in the control register. This signal can be used for controlling the LCD power supply, because LCDENB is set to "L" by RESET. Power supply pin Ground No connection
Number of pins
VD<7:0>
Output
8
CP
Output
1
LP LCD interface FLM
Output
1
Output
1
M
Output
1
LCDENB Output VDD Others VSS N.C
1 7 7 10
DIFFERENCE BETWEEN M66273FP AND M66272FP
The M66273FP is an adv anced product f rom the M66272FP at the point of MPU interf ace and timing specif ications. LCD display f unctions are the same with the M66272FP. The f ollowing shows dif f erence between the M66273FP and the M66272FP without timing specif ications. Ref er to the later item about timing specif ications and detail specif ications.
Specif ication Pin f unction
M66273FP WAITCNT input ( WAIT control input)
M66272FP SWAP input ( Bus swap input)
WAIT output control
It is capable of selecting WAIT output trigger input. WAIT output change to "L" at the timing of the falling In case of fixed WAITCNT input, change WAIT to "L" at the edge of overlapping with MCS and RD or LWR/HWR. timing of the falling edge of overlapping with MCS and RD or LWR/HWR, and in case of using WAITCNT input, change WAIT to "L" at the timing of the falling edge of WAITCNT on MCS="L".
Access to control register
Use IOCS or MCS pins for chip select of control register. (capable of controlling VRAM and control register by MCS pin.)
Use IOCS pin for chip select of control register.
Bus swap f unction Set by SWAP register.
Set by SWAP pin.
4
MITSUBISHI
M66273FP
Ver.3.1 Dec,1999
LCD CONTROLLER with VRAM
OUTLINE
The M66273 is a graphic display only controller for displaying a dot matrix type STN-LCD. * LCD display mode It is capable of displaying six types of LCD by combining the panel configuration, binary/gray scale, LCD display data bus width.
LCD display Display Panel Binary/ configuration gray scale data mode 1 2 3 4 5 6
Displayable LCD size Equivalent to 640 x 240 Equivalent to 320 x 240
Equivalent to 320 x 240 x 2 screens Equivalent to 320 x 120 x 2 screens
* Cycle steal system Cycle steal system is interact method of transforming display data for LCD from VRAM and accessing VRAM from MPU on the basic cycle (MAINCLK) of internal operation. Basic timing is two clocks of MAINCLK, and assign first clock to the access from MPU to VRAM and second clock to the transfer of display data from VRAM to LCD. In accessing VRAM from MPU, output WAIT. In case of fixed WAITCNT input, change WAIT to "L" at the timing of the falling edge of overlapping with MCS and RD or LWR / HWR,and in case of using WAITCNT input, change WAIT to "L" at the timing of the falling edge of WAITCNT on MCS="L", And return to "H" at synchronizing with rising edge of M PUCLK after internal processing. For the cycle steal system, this IC provides a cycle steal control function to improve data transfer efficiency in a line. This func-tion gains access with the cycle steal system by taking WAIT for MPU during the display term with necessity for the display data transfer from built-in VRAM to LCD. On the other side, it does not output WAIT for keeping throughput of MPU during horizontal synchronous term (idle running term) with no necessity for the display data transfer from VRAM to LCD side. In detail,refer to "Description of cycle steal". * Output to LCD side LCD display data VD<7:0> is output in parallel per 4 bits or 8 bits in synchronization with the rising edge of CP. Pin VD differs depending on the display mode. Single scan 4-bit transfer 8-bit transfer Dual scan 4-bit transfer VD<7:4> VD<3:0> Display mode
1 3
4bit Binary Single scan Gray scale Binary Gray scale 8bit 4bit 8bit Dual scan 4bit 4bit
* Control register When accessing the control register from MPU, use pins IOCS, LWR, RD, A<7:0> and D<7:0>, or MCS, LWR, RD,A<14:0> and D<7:0> (However, use D<15:0> only when 16-bit MPU controls the LCD module built-in support function.) Refer to Table-1, setting of control input. The IC contains the following registers as control registers. Operation control Gray scale pattern table R1 to R11 R17 to R80
Supporting LCD module built-in type R12 to 14 or R15 to 16
* VRAM This IC has a built-in 19200-byte VRAM which is equivalent to two screens of 320 x 240 dots LCD. When accessing VRAM from MPU, use pins MCS, HWR, LWR, RD, BHE, A<14:0> and D<15:0>. Use of MPUSEL input can support both 8/16 bit MPU. Refer to table-2 to 6, VRAM specifications for 8/16 bit MPU and input setting in access. The VRAM address settable range is restricted depending on the panel configuration, as follows. VRAM address settable range * When single scan mode *A<14:0>=0000 to 4AFFH --- 19200 byte 0000H VRAM 4AFFH * When dual scan mode *For the 1st screen --- A<14:0>=0000 to 257F H --- 9600 byte *For the 2nd screen --- A<14:0>=2580 to 4AFFH --- 9600 byte 0000H VRAM for the 1st screen 257FH 2580H VRAM for the 2nd screen 4AFFH
VD<7:0>
2 4
VD<3:0>
5 6
When display data for a line has been sent, LP outputs data in synchronization with the falling edge of MAINCLK. The IC enables adjustment to an optimum value of the frame frequency as requested from the LCD PANEL side by adjusting pulse width of LP with the LPW register value. FLM is output when the display data for the first line has been sent. M output is an LCD alternating signal for driving LCD with alternating current. M output cycles can be set in lines with the M output cycle variable register and is available to prevent LCD from deterioration. * Gray scale display function Gray scale display can assign 2-bit VRAM data to a picture element of LCD display to show the display density at four levels. Gray scale display pattern tables 0 and 1 (4 x 4 matrix x 16 patterns x 2 medium gray scale), consisting of SRAM of 64 bytes in total, can set any gray scale display pattern. In detail,refer to "Description of gray scale function". * Application to reflective color type LCD The above gradation display function is available to control about four display colors on the reflective color type LCD with ECB (Electrically Controlled Birefringence).
5
MITSUBISHI
M66273FP
Ver.3.1 Dec,1999
LCD CONTROLLER with VRAM
COMBINATIONS OF CONTROL INPUT PINS ON THE MPU INTERFACE
Tables 1 to 6 show input setting conditions for access to the control register and VRAM from the MPU side. (1) Access to the control register For data, D<7:0> is used. (Only when 16bit MPU is used to control the LCD module built-in system, D<15:0> is used for data.) Table-1 IOCS MCS LWR RD L L H H H (2) Write to VRAM (2-1) For use of 8bit MPU (Set as follow: MPUSEL="L", BHE=HWR="H") Table-2
MPU SEL MCS BHE A<0> HWR LWR Odd address Even address Valid data bus width for MPU
A<14:0> 0000H to 009EH 0000H to 009EH 5000H to 509EH 5000H to 509EH IOCS control MCS control
Operation Writes to control register Reads from control register Writes to control register Reads from control register Invalid
H H L L H
L H L H X
H L H L X
L
L
H
H
L H X X
H
L H X
Invalid Write Invalid
Write Invalid Invalid
8bit
(2-2) For use of 16bit MPU - 1 (For MPU controlling byte access with A<0> and BHE, set as follow: MPUSEL=HWR="H") Table-3
MPU SEL MCS BHE A<0> HWR LWR
Upper byte Write Invalid Write Invalid Invalid Invalid
Lower byte Write Invalid Invalid Invalid Write Invalid
Valid data bus width for MPU
H
L
L
L
H
H L H H H X X
L H L H L H L H X
16bit Upper 8bit Lower 8bit
(2-3) For use of 16bit MPU - 2 (For MPU controlling byte access with LWR and HWR, set as follow: MPUSEL=BHE="H", A<0>="L") Table-4
MPU SEL MCS BHE A<0> HWR LWR
Upper byte Write Write Invalid Invalid
Lower byte Write Invalid Write Invalid
Valid data bus width for MPU
H
L
H
L
L
L H L H X
16bit Upper 8bit Lower 8bit
H H (3) Read from VRAM X
(3-1) For use of 8bit MPU (Set as follows: MPUSEL="L", BHE="H") Table-5
MPU SEL MCS BHE A<0>
RD L H X
Odd address Even address Invalid Read Invalid Read Invalid Invalid
Valid data bus width for MPU
L
L
H
L H X
8bit
H
(3-2) For use of 16bit MPU (Set as follow: MPUSEL="H") Table-6
MPU SEL MCS BHE A<0>
RD L H X
Upper byte Read Invalid
Lower byte Read Invalid
Valid data bus width for MPU
H
L H
X
X
16bit
Notes : Combinations except for the above cause malfunction. Be sure to make settings according to the above combinations. : X=either "L" or "H" 6
MITSUBISHI
M66273FP
Ver.3.1 Dec,1999
LCD CONTROLLER with VRAM
CONTROL REGISTER
M66273 is equipped with 80 types of built-in control registers. For operation control Only for LCD module built-in system For gradation pattern table R1 to R11 R12 to R14, or R15 to R17 R17 to R80 IOCS, LWR, RD, A<7:0> and D<7:0>, or MCS, LWR, RD, A<14:0> and D<7:0> are used for setting from the MPU to control register. And for address in IOCS control,use A<7:0>=00H to 9EH,and in MCS control, use A<14:0>=5000H to 509EH. (However, D<15:0> is to be used only when registers R15 and R16 only for LCD module built-in system are used.)
(1) Types of control registers
* List of registers for operation control Types of register No. R1 R2 R3 R4 R5 R6 R7 R8 R9 2nd screen display start address Name Basic operation mode LCD output mode Number of horizontal display characters Horizontal synchronous pulse width Cycle steal enable width Number of vertical lines 1st screen display start address Address Address
(ICOS control) (MCS control)
Data D2
DISP
R/W D1
REV
Reset 00H 00H 28H 04H 02H 78H 00H 00H
A<7:0> 00H 02H 04H 06H 08H 0AH 0CH 0EH 10H 12H 14H
D6 D5 D4 D3 A<14:0> D7 DIV 5000H RESET IDXON WAITCSWAP 5002H CR 5004H LPW 5006H CSW 5008H SLT 500AH 500CH 500EH 5010H 5012H 5014H SA1L SA1H SA2L SA2H MT
D0
LCDE
DUAL GRAY
4/8
R/W R/W W W W W
D0 0 D0 0
R/W
R/W W
80H 25H 00H
R10 R11 M output frequency variable
* List of registers only for LCD module built-in type support function (For 8bit MPU only) R12 VRAM address index R13 R14 Data port (For 16bit MPU only) Types of register No. Name Address Address
(ICOS control) (ICOS control)
16H 18H 1AH
5016H 5018H 501AH
IDX8L IDX8H DP8
R/W R/W
00H 00H
Undetermined
Data D0 D14 D1 IDX16 D15 DP16 D0 0 D0 R/W R/W R/W
Reset 0000H
Undetermined
A<7:0> 1CH 1EH
A<14:0> D15 501CH 501EH
R15 VRAM address index R16 Data port
* List of registers for gray scale pattern table Types of register No. R17 R18 to R47 R48 R49 R50 to Name Gray scale pattern 0-1 Gray scale pattern 0-2 to Gray scale pattern 0-31 Gray scale pattern 0-32 Gray scale pattern 1-1 Gray scale pattern 1-2 to Address Address
(ICOS control) I C O S c o n t r o l 9 (
Data D7 D6 D5 D4 D3 D2 D1 D0
FRC0-1-2 FRC0-1-4 FRC0-1-1 FRC0-1-3
A<7:0> 20H 22H to 5CH 5EH 60H 62H to 9CH 9EH
A<14:0> 5020H 5022H to 505CH 505EH 5060H 5062H to 509CH 509EH
R/W
Reset
to
FRC0-16-2 FRC0-16-4 FRC1-1-2 FRC1-1-4
to
FRC0-16-1 FRC0-16-3 FRC1-1-1 FRC1-1-3
R/W
Undetermined
to
FRC1-16-2 FRC1-16-4
to
FRC1-16-1 FRC1-16-3
R/W
Undetermined
R79 Gray scale pattern 1-31 R80 Gray scale pattern 1-32
7
MITSUBISHI
M66273FP
Ver.3.1 Dec,1999
LCD CONTROLLER with VRAM
(2) Description of registers
Address is listed for ICOS control. Incase of MCS control,set to address adding 50H to upper 7 bit (50**H).
[R1] Basic operation mode
Set the Basic operation mode Address R/W D7 0 1 D6 0 1 RESET Reset OFF Reset ON *Set to decide whether or not the function only for LCD module built-in system is used. *Set Index mode OFF for reset. Function *Software reset. Restriction *Surely return to reset off after reset on. And then, can't set another bits (D6 to D0) at the same time. Reset
0
IDXON Index mode OFF Index mode ON DIV D4 D3 0 0 0 1 1 0 1 1 0 0 DISP Display OFF Display ON REV Normal display Reverse display LCDE LCDENB="0"output LCDENB="1"output
0
D5 0 0 0 0 1 00H R/W D2 0 1 D1 0 1 D0 0 1
Division of MPUCLK input 1 1/2 division 1/4 division 1/8 division 1/16 division
*Set the division of MPUCLK input to set the reference clock cycle (MAINCLK) for internal operation. *Resetting does not divide MPUCLK.
*Don't set except for the settings in the table at left. 000
*Control display ON/OFF of LCD. *In the reverse mode with REV (D1) set to "1", "1" is output to display data VD with DISP="0". *Reset sets display OFF. *Controls normal/reverse of LCD display. *Resetting sets normal display.
0
0
*Sets the data output from the LCDENB output pin. *Resetting outputs "0" (Vss potential) to the LCDENB output pin. *This function is prepared for controlling the apply voltage to LCD. When the power supply is turned ON after registers have been completely set, set this LCDE to "1" to apply the LCD voltage. Conversely for turning OFF the power supply to the system, set the LCDE to "0" to turn OFF the LCD voltage. This prevents abnormal DC voltage from being applied to the LCD. This function depends on the LCD functions. Use the function, if necessary.
0
8
MITSUBISHI
M66273FP
Ver.3.1 Dec,1999
LCD CONTROLLER with VRAM
[R2] MPUI/LCD mode
Set the display data output mode on the LCD side. Address R/W D7 , D6 are not used. D5 WAITC Function *To read R2, "0" is output to D7 , D6.
*Set to select trigger signal of WAIT output. *When setting WAITC to "0", change WAIT to "L" at timing of falling edge of overlapping with MCS and RD or LWR and HWR. And return to "H" at synchronization with the rising edge of MPUCLK offer internal processing. *When setting WAITC to "T", change WAIT to "L" at timing of falling edge of WAITCNT on MCS="L".And return to "H" at synchronization with rising edge of MPUCLK after internal processing. *Output WAIT only when requested access from MPU to VRAM is gained during cycle steal access. *Resetting set WAITC ="0".
Restriction
Reset 0
MCS and RD or H/LWR 0 control 1 WAITCNT control
*set when register is initialized. *When setting to "0",connect WAITCNT input to VSS or VDD.
0
D4 02H R/W
SWAP
0 Order of upper/lower byte 1 Order of lower/upper byte
*When selecting 16 bit MPU, set SWAP to "0" to transfer VD in order of Upper/Lower byte of MPU data bus,reversally set to "1" in order of Lower/Upper byte. *When selecting 8 bit MPU, set to "0" *Even if setting to "1", use D<7:0> to access to register of 8 bit width. *Resetting set SWAP="0". *To read R2, "0" is output to D3. *Set the LCD panel configuration. *Resetting sets the 1 screen driving panel.
*set when register is initialized. 0
D3 is not used. D2 DUAL
0 *set when register is initialized.
0 1 screen driving panel 1 2 screen driving panel D1 GRAY
0
0 Binary display mode 1 Gray scale display mode D0 0 1 4/8 4bit transfer 8bit transfer
*Set the LCD display mode (binary or gray scale). *Resetting sets the binary display mode.
*set when register is initialized.
0
*Set the transfer path width of the LCD display data path VD. *Resetting sets 4bit transfer.
*set when register is initialized.
0
9
MITSUBISHI
M66273FP
Ver.3.1 Dec,1999
LCD CONTROLLER with VRAM
[R3] Number of horizontal display characters
Address R/W CR Function *Sets the number of hori-zontal Number of LCD display dots Number of display characters per line. D7 to D0 characters Binary display Gray scale display *Resetting sets "28H" (=40 characters). 00H 04H W 01H 02H 1 2 8 16 4 8 Restriction *For CR, maximum of 255 characters can be set. *In display modes 2, 3 , 4 and 6 , the number of even cha-racters can be set. Reset
28H
FFH
255
2040
1020
(Note) Definition of the number of characters The number of display characters means data corresponding to 1byte of VRAM. One character : In the case of binary, one character means 8dots of LCD display. In the case of gray scale display, one character means 4dots of LCD display (because 2bits of VRAM corresponds to 1dot of LCD display).
[R4] Horizontal synchronous pulse width
Address R/W LPW Number of D7 to D0 characters 00H 06H W 01H 02H 2 Function *In the unit of characters, set the width of horizontal synchronous pulse generated per line. Horizontal synchronous pulse is output from the LP pin and is used for serial/parallel conversion of displayed data. Adjustment of LPW can set the frame frequency to an optimum value. The LP output pulse actually generated takes the value(LPW setup value - 2CP), taking into account the CP output timing. Only in the case of display mode 4, however, the LP output pulse takes the value (LPW set value - 1CP). *Resetting sets "04H" (= 4 characters). Restriction *In display modes 2 , 3 , 4 and 6 , only the number of even characters can be set. *In display modes 1 and 5 , set LPW to 02H or more. *In display modes 2 , 3 , 4 and 6 , set LPW to 04H or more. Reset
04H
FFH
255
[R5] Cycle steal enable width
Address R/W CSW Number of D7 to D0 characters 00H 08H W 01H 02H 1 2 Function *In unit of characters, set the period of access by the cycle steal system near the end of the horizontal synchronous portion set with LPW. *With CSW=LPW, gain access by the permanent cycle steal system. *Resetting sets "02H" (=2 characters). Restriction Reset *Set CSW to the LPW set value or less. *In display modes 2, 3 , 4 and 6 , only the number of even 02H characters can be set. *In display modes 1 and 5 ,set CSW to 01H or more. *In display modes 2 , 3 , 4 and 6 , set CSW to 02H or more.
FFH
255
[R6] Number of vertical lines
Address R/W Number of D7 to D0 vertical lines 00H 0AH W 01H 02H 2 4 SLT Function *Sets the number of lines displayed in the direction of LCD vertical line. *SLT also sets the LCD display driving duty. *In dual scan mode, the actual number of displayed lines is given by SLT x 2 screens. *Resetting sets "78H" (=240 lines). Restriction *Be sure to set SLT according to the number of LCD display lines. *For SLT, a maximum of 510 even lines can be set. Reset
78H
FFH
10
510
MITSUBISHI
M66273FP
Ver.3.1 Dec,1999
LCD CONTROLLER with VRAM
[R7, R8] 1st screen display start address
Address R/W SA1H 0CH
(SA1L)
Function SA1L 1st screen display start address 0000H 0002H 0004H *Sets the 1st screen display start address. *The display start address is determined by writing data into SA1H. *Reading SA1H outputs "0" to D7. *Resetting sets "0000H".
Restriction
*At the display start add-ress, even addresses can only be set. * For single scan; 0000H to 4AFEH * For dual scan; Sets 0000H to 257EH. Settings except for the above must not be made. *To modify the display start address, be sure to respecify in order of SA1LSA1H even when only SA1L is modified.
Reset
D7 D6 to D0 D7 to D0 00H 00H R/W 00H 00H 02H 04H
00H
0EH
(SA1H)
4AH
FEH
4AFEH
00H
[R9, R10] 2nd screen display start address
Address R/W SA2H 10H
(SA2L)
Function SA2L 2nd screen display start address 2580H 2582H 2584H *Used for dual scan mode only to set the 2nd screen display start address. *The display start address is determined by writing data into SA2H. *Reading SA2H outputs "0" to D7. *Resetting sets "2580H".
Restriction *At the display start address, only even addresses can be set, and; *Can set 2580H to 4AFEH. Settings except for the above must not be made. *To modify the display start address, be sure to respecify in order of SA2L - SA2H even when only SA2L is modified.
Reset
D7 D6 to D0 D7 to D0 25H 25H R/W 25H 80H 82H 84H
80H
12H
(SA2H)
4AH
FEH
4AFEH
25H
[R11] M output cycle variable
Address R/W MT D7 to D0 00H 14H W 01H 02H Function Output cycle of M signal Makes toggle change every frame. Makes toggle change every line (=1LP). Makes toggle change every 2 lines. *Sets the output cycle of M signal output from the M terminal. With MT=01H, for example, M signal repeatedly reverses (toggles) every line. *Resetting sets "00H". *It is recommended to set this register to an optimum value according to the LCD specification. Restriction Reset
00H
FFH
Makes toggle change every 255 lines.
11
MITSUBISHI
M66273FP
Ver.3.1 Dec,1999
LCD CONTROLLER with VRAM
[R12, R13] VRAM address index (8bit MPU only)
Address R/W IDX8H 16H
(IDX8L)
Function IDX8L VRAM address to access 0000H 0001H 0002H
Restriction *VRAM addresses to *VRAM address index register only for LCD access can be set to module built-in system. Sets the VRAM 0000H to 4AFFH. address to access. *Since IDX8H and IDX8L are independent from Settings except for the above must not be made. each other, either one of the register values can also be set and modified. In addition, automatic increments are made for consecutive addresses. *Reading IDX8H outputs "0" to D7. *Resetting sets "0000H".
Reset
D7 D6 to D0 D7 to D0 00H R/W 00H 00H 00H 01H 02H
00H
18H
(IDX8H)
00H
4AH
FFH
4AFFH
[R14] Data port (8bit MPU only)
Address R/W DP8 D7 to D0 1AH R/W Function Data port (8bit) *Data port register only for LCD module builtin type support additional functions. Via this register, 8bit data is read/written between MPU and VRAM. *Completion of access to DP8 increments the IDX8H and IDX8L values by +1. * Resetting outputs undetermined data. Restriction Reset
XXH
(Undetermined)
[R15] VRAM address index (16bit MPU only)
Address R/W IDX16 D15 D14 to D0 0000H 1CH R/W 0002H 0004H Function VRAM address to access 0000H 0002H 0004H *VRAM address index register only for LCD module built-in type support addi-tional functions. Sets the VRAM address to access. *Automatically incremented for consecu-tive addresses. *Reading IDX16 outputs "0" to D15. *Resetting sets "0000H". Restriction *VRAM address to ac-cess can be set to 0000H to 4AFEH. Settings except for the above must not be made. *Set the VRAM address with D<14:1> and fix it to D<0>=0. Reset
0000H
4AFEH
4AFEH
Note : With SWAP="1" set, set the byte-swapped data for the VRAM address to access. (Set low order bytes of VRAM address to D<15:8> and set high order bytes of VRAM address to D<7:0>.)
[R16] Data port (16bit MPU only)
Address R/W DP16 D15 to D0 1EH R/W Function Data port (16bit) *Data port register only for LCD module builtin type support additional functions. Via this register, 16bit data is read/ written between MPU and VRAM. *Completion of access to DP16 incre-ments the IDX16 value by +1. *Resetting outputs undetermined data. Restriction Reset
XXXXH
(Undetermined)
Note : Registers R12 to R16 are used only for LCD module built-in system. Register setting is not needed if these functions are not used.
12
MITSUBISHI
M66273FP
Ver.3.1 Dec,1999
LCD CONTROLLER with VRAM
[R17 to R80] Gradation patterns 0-1 to 32 and 1-1 to 32
Address R/W Function Register No. 20H to 5EH Name Address *Sets data of gradation pattern 0. D3 to D0 A<7:0> D7 to D4 Gradation pattern 0 FRC0-1-2 FRC0-1-1 provides 16 patterns of 20H 4 x 4 matrix. FRC0-1-4 FRC0-1-3 22H Data to 5CH 5EH Address to to Restriction Reset *Set gradation patterns when the register is initialized. *When access to R17 to R80, must be set XXH (UndeterDISP=OFF. mined) Can't access to R17 to R80 on DISP=ON. *All registers R17 to R80 must be set.
R17 Gray scale pattern 0-1 R/W R18 Gray scale pattern 0-2 to to
R47 Gray scale pattern 0-31 R48 Gray scale pattern 0-32 Register No. 60H to 9EH Name
FRC0-16-2 FRC0-16-1 FRC0-16-4 FRC0-16-3
R49 Gray scale pattern 1-1 R/W R50 Gray scale pattern 1-2 to to
*Sets data of gradation pattern 1. D3 to D0 A<7:0> D7 to D4 Gradation pattern 1 FRC1-1-2 FRC1-1-1 60H provides 16 patterns of 4 x 4 matrix. FRC1-1-4 FRC1-1-3 62H Data to 9CH 9EH to to
XXH
(Undetermined)
R79 Gray scale pattern 1-31 R80 Gray scale pattern 1-32
FRC1-16-2 FRC1-16-1 FRC1-16-4 FRC1-16-3
Gray scale pattern 0-1 Gray scale pattern table 0 or 1 Register running Nos. 1 to 32
FRC0-1-1 Gray scale pattern table 0 or 1 Number of patterns : 1 to 16 Number of lines : 1 to 4
Gray scale pattern setting example Gray scale pattern 0-1 = 48H Gray scale pattern 0-2 = 12H 1st frame 1st line 2nd line 3rd line 4th line FRC0-1-1 FRC0-1-2 FRC0-1-3 FRC0-1-4
Note : Registers R17 to R80 are used to set gray scale patterns for gray scale display. Register setting is not needed for binary display.
13
MITSUBISHI
M66273FP
Ver.3.1 Dec,1999
LCD CONTROLLER with VRAM
Description of LCD display Relationships between control register setting and LCD display
1 horizontal line CR LPW CSW
SA2H,L SA1H,L
2nd screen 1st screen
SLT Control register setting conditions *1st screen drive Binary --- (CR x 8) x SLT Gray scale --*2nd screen drive Binary --- (CR x 8) x (SLT x 2) Gray scale ---
LCD screen to be display ed
<=153600 dots <= 76800 dots <=153600 dots <= 76800 dots
1 horizontal line Number of horizontal display characters CR Horizontal synchronous pulse width LPW
x Number of vertical lines SLT
MAINCLK
1 2 3 m-2 m-1 m 1 2
CP VD LP (1) Time required for processing 1 horizontal line (TH) 2 x (CR+LPW) TH = *Display modes 1 and 5 fMAINCLK *Display mode
2 , 3 , 4 and 6 Data not determined
TH =
1 x (CR+LPW) fMAINCLK
CR,LPW,CSW : Unit of characters SLT : Unit of even lines fMAINCLK : Frequency of MAINCLK for internal operation Adjustment of LPW can set the number of frame frequencies requested on the LCD panel side to an optimum value.
(2) Time required for processing 1 frame (TFR) TFR = TH x SLT
Relationships between control register setting and LCD display
14
MITSUBISHI
M66273FP
Ver.3.1 Dec,1999
LCD CONTROLLER with VRAM
Relationships between display start address and LCD display
Example) When 8bit MPU is used : With display start address = 1000H
0000H 0001 1000H 1001H
VRAM
LCD screen
~ ~
1000H
1001H
~ ~
4AFE H 4AFFH
~ ~
4AFE H 4AFFH 0000H
0001H
~ ~
*The data of display start address (SA1H, L, SA2H, L) is displayed upper left in the LCD. *The display start address is loaded from register in frames. Relationships between display start address and LCD display
Relationships between VRAM address, data and LCD display
VRAM address, data For 16bit MPU A<14:0> D<15:0> For 8bit MPU A<14:0> D<7:0> 0000H E41BH 0000H E4H D15 D14 D13 D12 D11 D7 D6 D5 D4 D3 1 1 1 0 0 a b c d e 0001H 1BH D4 D3 D4 D3 1 1 l m 16bit MPU (when setting SWAP = "0") 8bit MPU
D10 D2 1 f
D9 D1 0 g
D8 D0 0 h
D7 D7 0 i
D6 D6 0 j
D5 D5 0 k
D2 D2 0 n
D1 D1 1 o
D0 D0 1 p
A<14:0> D<15:0> A<14:0> D<7:0>
2580H FA50H 2580H FAH D15 D14 D13 D12 D11 D7 D6 D5 D4 D3 1 1 1 1 1 A B C D E 2581H 50H D4 D3 D4 D3 1 0 L M
D10 D2 0 F
D9 D1 1 G
D8 D0 0 H
D7 D7 0 I
D6 D6 1 J
D5 D5 0 K
D2 D2 0 N
D1 D1 0 O
D0 D0 0 P
LCD display Display mode Display mode
1 2
VD3 VD2 VD1 VD0 VD3 VD2 VD1 VD0 VD7 VD6 VD5 VD4 VD3 VD2 VD1 VD0 1 a 1 b 1 c 0 d 0 e 1 f 0 g 0 h
Display mode Display mode
3 4
VD3 VD2 VD1 VD0 VD3 VD2 VD1 VD0 VD7 VD6 VD5 VD4 VD3 VD2 VD1 VD0 a b c d e f g i k h j l LCD screen m n o p
LCD screen
Display mode
5
VD7 VD6 VD5 VD4 VD7 VD6 VD5 VD4 1 a 1 b 1 c 0 d 0 e 1 f 0 g 0 h
Display mode
6
VD7 VD6 VD5 VD4 VD7 VD6 VD5 VD4 a b c d e f g i k m h j l n 1st screen of LCD o p
1st screen of LCD VD3 VD2 VD1 VD0 VD3 VD2 VD1 VD0 1 A 1 B 1 C 1 D 1 E 0 F 1 G 0 H
VD3 VD2 VD1 VD0 VD3 VD2 VD1 VD0 A B C D E F G I K M H J L N 2nd screen of LCD O P
2nd screen of LCD
: Gray scale display image
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MITSUBISHI
M66273FP
Ver.3.1 Dec,1999
LCD CONTROLLER with VRAM
Relationships between SWAP setting and LCD display
When 16bit MPU is in use, setting the SWAP register can modify the sending order of LCD display data in bytes. SWAP setting 0 1
For D<15:0>, sends VD in order of upper / lower bytes. For D<15:0>, sends VD in order of lower / upper order bytes.
VRAM data
D15 D14 D13 D12 D11 D10 D9 1 1 1 0 0 1 0 High order byte = E4H
D8 0
D7 0
D6 0
D5 0
D4 1
D3 1
D2 0
D1 1
D0 1
Low order byte = 1BH
*Setting SWAP = "0" D15 to D8D7 to D0
*Setting SWAP = "1" D7 to D0D15 to D8
1110010000011011 E4H LCD screen 1BH
0001101111100100 1BH LCD screen E4H
Relationships between LCD display mode and VD pin
Single scan mode 4bit parallel Display mode VD3 VD2 VD1 VD0
1
,
3
Dual scan mode 4bit parallel Display mode VD7 VD6 VD5 VD4
5
,
6
LCD screen
1st screen of LCD VD3 VD2 VD1 VD0
Single scan mode 8bit parallel Display mode VD7 VD6 VD5 VD4 VD3 VD2 VD1 VD0
2
,
4
2nd screen of LCD
LCD screen
16
MITSUBISHI
M66273FP
Ver.3.1 Dec,1999
LCD CONTROLLER with VRAM
Output signal on the LCD side
Example) Assuming 320 x 240 dots LCD is used in display mode 1 (CR = 40 characters, LPW = 2 characters, SLT = 240 lines, DIV = division value 1, MT = 1) (1) Output per line MAINCLK
80 1 2 79 80 1 2 Output each time one piece of display data is transferred. 4bit transfer Output when display data for a line is comp-letely sent.
CP VD<3:0> LP (2) Output signal per screen
239 240 1 239 240 1
LP FLM M
Output when display data in the 1st line is completely sent. Output reverse period of M signal can be set with the MT register.
(3) LCDENB output signal MAINCLK LCDENB
(4) Reset to 1st screen/1st line RESET MAINCLK LCDENB LP FLM M CP 1st screen/1st line (5) 1st line to 2nd line MAINCLK LP FLM M
76 77 78 79 80 1 2 3 4 5 6 7 8 1 2 3 4 5 6
"L"
CP 1st line (6) 1st screen/240th line to 2nd screen/1st line MAINCLK LP FLM M
76 77 78 79 80 1 2 3 4 5 6 7 8
2nd line
"L"
CP 1st screen/240th line 2nd screen/1st line
17
MITSUBISHI
M66273FP
Ver.3.1 Dec,1999
LCD CONTROLLER with VRAM
Display data Access to VRAM transfer from from MPU VRAM to LCD
Description of cycle Steal Basic timing
The basic timing for internal operation of the M66273 adopts 2 clocks of MAINCLK as a basic cycle to assign the 1st clock and 2nd clock to access from MPU to VRAM and transfer of display data from VRAM to the LCD side, respectively. MAINCLK is reference clock for internal operation inputting division of MPUCLK and reference with rising edge of MPUCLK.
MPU
LCD
MAINCLK Basic cycle
MPU access execution cycle (WAIT output period)
Writing/reading to/from VRAM in the display section takes, Best case = 0.5tc(MAINCLK) + 1tc(CLK), Worst case = 2.5tc(MAINCLK) + 1tc(CLK), depending on the internal cycle steal status when access request from MPU starts.
LCD access cycle MPU access cycle
Basic timing In this case, tc(CLK) = MPUCLK cycle time, tc(MAINCLK) = MAINCLK cycle time.
LCD access cycle
MPU access cycle
LCD access cycle
MAINCLK Ex.1 ) Assuming set to WAITCNT = "0" and MCS input is faster than RD or LWR/HWR input.(1/4 division) Best case (When access start in LCD access cycle.) MCS LWR WAIT
Start of WAIT in synchronization with falling edge of LWR. MPU access execution cycle
0.5tc (MAINCLK) 1tc (CLK)
Release of WAIT in synchronization with rising edge of MPUCLK.
MPUCLK
Worst case (When access start in MPU access cycle.) MCS LWR
1.5tc (MAINCLK)
MPU access execution cycle
1tc (CLK)
WAIT
Start of WAIT in synchronization with falling edge of LWR.
MPUCLK
Release of WAIT in synchronization with rising edge of MPUCLK.
Ex.2 ) Assuming set to WAITC = "1".(1/4 division) Best case (When access start in LCD access cycle.) MCS WAITCNT LWR WAIT
Start of WAIT in synchronization with falling edge of WAITCNT. MPU access execution cycle
0.5tc (MAINCLK) 1tc (CLK)
Release of WAIT in synchronization with rising edge of MPUCLK.
MPUCLK
Worst case (When access start in MPU access cycle.) MCS WAITCNT LWR
1.5tc (MAINCLK)
MPU access execution cycle
1tc (CLK)
WAIT
Start of WAIT in synchronization with falling edge of WAITCNT.
Release of WAIT in synchronization with rising edge of MPUCLK.
MPUCLK MPU access execution cycle
18
MITSUBISHI
M66273FP
Ver.3.1 Dec,1999
LCD CONTROLLER with VRAM
Description of cycle steal control function
The M66273 provides the cycle steal control function to efficiently carry out one-line data processing. In the display section where display data requires to be transferred from built-in VRAM to the LCD side, this function adopts a cycle steal system to gain access to the MPU while putting the MPU in WAIT. In a horizontal synchronous section where display data does not require to be transferred from VRAM to the LCD side, this function does not output WAIT in the section to avoid reducing the MPU throughput. However, since malfunction is restrained near the termination of horizontal synchronous section, the CSW register should be surely set to provide a period of access by the cycle steal system. (It need to set at least 1 cycle of MPU bus timing.)
Example) Assuming 320 x 240 dot LCD in display mode 1 . 1 horizontal line LP
1 2 3 78 79 80 1 Output when 1-line display data is comp-letely sent. Output each time one piece of display data is transferred. 4bit transfer
CP VD<3:0> Set with the CR register
Section where data requires to be transferred from display section = VRAM to the LCD side (cycle steal system)
Set with the LPW register
Section where data does not require to be transferred from horizontal section = VRAM to the LCD side
CSE
Set with the CSW register
Putting MPU in WAIT according to cycle steal access.
Gains access at the MPU bus timing without putting MPU in WAIT.
Provides a timing for setting CSE to OHO to put MPU in WAIT.
WAIT
Without putting MPU in WAIT
19
MITSUBISHI
M66273FP
Ver.3.1 Dec,1999
LCD CONTROLLER with VRAM
Set the same pattern for each 4 or 8 frames period in 16 frames. So enable to decrease frame numbers of gray scale period. Still more, set the same gray scale pattern table in frame unit, so enable to display thinned-out frame method. When thinned-out 1frame from continuous 4frames, the following are example of setting pattern table.
1st frame 2nd frame 3rd frame 4th frame
Description of gray scale function
Set gray scale mode by register (GRAY= "1"). Gray scale assign 2bits of VRAM to 1dot of LCD and displaying 4density. ex.) for 8bit-MPU 1 Address VRAM data D7 D6 D5 D4 D3 D2 D1 D0 Pack C1 C0 C1 C0 C1 C0 C1 C0 C1 0 0 1 1 C0 0 1 0 1 Contents of display Display OFF Followed gray scale pattern table 0 Followed gray scale pattern table 1 Display ON D7 VRAM data Gray scale Image of LCD Upper figure are image of gray scale display of LCD and VRAM data, actually controlling pseudo medium gray scale. Setting of gray scale pattern table Gray scale pattern table 0, 1 a used for controlling display density. It set to control register R17-R80 (SRAM configuration). Gray scale pattern set 16 patterns for 1 medium gray scale (1 pattern = 4dots x 4lines matrix). It need to set 32 patterns (64 byte) because 2 medium gray scale. Medium gray scale period is a maximum of 16 frames. Example of gray scale pattern The following are example of gray scale pattern. (Select 4dots from 1matrix, and each dot set equally in 1 period.)
1st frame 1st line 2nd line 3rd line 4th line 5th frame 6th frame 7th frame 8th frame 2nd frame 3rd frame 4th frame
4 Frames n+1 Address
Thinned-out frame
n Address
D0
D7
D0
11100100 3 2 1 0
t
11000110 3 0 1 2 Turn on frame When use thinned-out frame, distribute thinned-out equally, and avoid thinned-out continuous frame together. Gray scale function use the features of liquid crystal changed brightness by practical voltage. The following are gray scale patterns for each frame, and the relation between brightness and practical voltage.
White (0,0)
~
V0
Light gray (0,1)
~
V1
Gray (1,0)
~
V2
9th frame
10th frame
11th frame
12th frame
Black (1,1)
~
V3 Practical voltage
13th frame
14th frame
15th frame
16th frame
Brightness White Light gray
When VRAM data are following, VD output 1 for only
dot.
Pack C1 VRAM data 0
Gray scale pattern of 1st line in 1st frame Displaying data VD Gray scale pattern of 1st line in 2nd frame Displaying data VD 20
C0 1
C1 0
C0 1
C1 0
C0 1
C1 0
C0 1
Gray
Black 1 0 0 0 V0 0 0 1 0 V1 V2 V3 Practical voltage
MITSUBISHI
M66273FP
Ver.3.1 Dec,1999
LCD CONTROLLER with VRAM
Additional function for LCD module built-in system
(When use this function,recommend using ICOS to control I/O registers.) As all of the VRAM address in the M66273 are externally opened for addressing VRAM from MPU directly. When consider the LCD module built-in system, connect pins are increased. But the M66273 has an additional function for the LCD module built-in system by lessening connect pins. Access the internal VRAM through the VRAM address index register in this function. When use this function, need to set to IDXON = "0". When use this function and access to VRAM, it need to set to DISP = "0". * Method of accessing the internal VRAM The following show the process of accessing VRAM. Set fixed pins * Interface pins with MPU and I/O register for access to VRAM. 8bit MPU A<7:1> D<7:0> IOCS LWR Interface pins RD MPUCLK (19 pins) I/O register IDX8H, IDX8L DP8 16bit MPU A<7:1> D<15:0> IOCS LWR RD MPUCLK (27 pins) IDX16 DP16
* No use pins set the following. *HWR, MCS = "H", *BHE, A<0>, A<14:8> = "L" , D<15:8> = "L" (only for 8bit MPU), *MPUSEL, WAITCNT = "L" or "H", *WAIT, CSE = open, RESET = Power on reset or software reset. * (In case of software reset RESET = "H" : set) * Access the DP after writing the mode register DISP = "0". Always enable to access, because the display signal fixed "H" or "L" in DISP = "0" and a term is no wait access. * Select IDX8L, IDX8H (or IDX16), and write address (15bit) of VRAM as data. Enable to change IDXL and IDXH, even if either.
Set control register set to DISP = "0"
Discontinuous address
Access to VRAM address index register
Continuous address
Access to Data Port register
VRAM address is increased of +1.
* Select DP8 (or DP16), and read or write data to address of VRAM. Access DP and IDX without WAIT function. VRAM address is automatically increased of +1, when finished access to DP. After setting data of VRAM It doesn't need to set IDX, when access to continuous address.
Set to DISP = "1" * Set to DISP = "1", and displaying LCD.
* Example of access to VRAM (In case of 8bit MPU)
Increase to Addr=0001 Increase to Addr=1001 Increase to Addr=1002
IOCS LWR
R1 R1 00H R12 16H R13 18H R14 1AH R12 16H R13 18H R14 1AH R14 1AH R14 1AH R14 1AH R1 00H
A<7:0>
00H
D<7:0>
80H
40H
00H
00H
AAH
00H
10H
BBH
CCH
DDH
EEH
44H
Software IDXON=1 reset DISP=0 (initialize)
Write Data=AA to Addr=0000
Write Data=BB to Addr=1000
Write Data=CC to Addr=1001
Write Data=DD to Addr=1002
Write Data=EE to Addr=1003
IDXON=1 DISP=1
Discontinuous address
Continuous address
21
MITSUBISHI
M66273FP
Ver.3.1 Dec,1999
LCD CONTROLLER with VRAM
ABSOLUTE MAXIMUM RATINGS (Ta=-20 to +75 C unless otherwise noted)
Symbol VDD VI VO IO Pd Tstg Parameter Supply voltage Input voltage Output voltage Output current Power dissipation Storage temperature Condition Ratings -0.3 to +6.5 -0.3 to VDD+0.3 -0.3 to VDD+0.3 20 600 -55 to +150 Unit V V V mA mW
C
RECOMMENDED OPERATING CONDITIONS (Ta=-20 to +75 C unless otherwise noted)
Symbol VDD VSS VI VO Topr tr, tf Parameter Supply voltage Supply voltage Input voltage Output voltage Operating temperature Input rise, down time Normal input Schmidt trigger input 0 0 -20 +25 Condition 5.0V support 3.0V support Limits Min. Typ. 4.5 5.0 2.7 3.0 0 VDD VDD +75 500 5 Max. Unit 5.5 V 3.3 V V V
C
ns ms
ELECTRICAL CHARACTERISTICS (5V version support specifications, Ta=-20 to +75 C unless otherwise noted )
Symbol VIH VIL VT+ VTVOH VOL IIH IIL IOZH IOZL IDD(A) Parameter "H" input voltage "L" input voltage Threshold voltage in positive direction Threshold voltage in negative direction "H" output voltage "L" output voltage "H" input current "L" input current "H" output current in off status "L" output current in off status Average supply current in operation mode Supply current in static mode
D<15:0>
Condition Note 1 Note 2 VDD = 5.5V VDD = 4.5V VDD = 5.0V VDD = 4.5V VDD = 5.5V VDD = 5.5V VDD = 5.5V, VI = VDD or VSS fMAINCLK = 15MHz(MAX), Output =open VDD = 5.5V, IOCS, MCS = VDD Other VI = VDD or VSS fixed IOH = -4mA IOL = 4mA VI = VDD VI = VSS VO = VDD VO = VSS Display mode 1,2,3,4 Display mode 5,6
Limits Min. Typ. Max. Unit 3.85 5.5 V 0 1.35 2.3 3.7 V 1.25 2.3 4.1 0.4 10 -10 10 -10 60 mA 80 200 uA V uA uA
IDD(S)
Notes 1: Normal input terminal --- A<14:0>, D<15:0> 2: Schmidt trigger input terminal --- All input pins except for A<14:0>, D<15:0>
22
MITSUBISHI
M66273FP
Ver.3.1 Dec,1999
LCD CONTROLLER with VRAM
ELECTRICAL CHARACTERISTICS (3V version support specification, Ta=-20~+75 C unless otherwise noted )
Symbol VIH VIL VT+ VTVOH VOL IIH IIL IOZH IOZL IDD(A) "H" input voltage "L" input voltage Threshold voltage in positive direction Threshold voltage in negative direction "H" output voltage "L" output voltage "H" input current "L" input current "H" output current in off status "L" output current in off status Average supply current in operation mode Supply current in static mode
D<15:0>
Parameter Note 1 Note 2 VDD = 3.3V VDD = 2.7V VDD = 3.0V VDD = 2.7V VDD = 3.3V VDD = 3.3V
Condition
Limits Unit Min. Typ. Max. 2.31 3.3 V 0 0.81 1.27 0.45 IOH = -4mA IOL = 4mA VI = VDD VI = VSS VO = VDD VO = VSS Display mode 1 to 4 Display mode 5 and 6 2.3 0.4 10 -10 10 -10 25 mA 35 200 uA 2.18 1.5 V V uA uA
VDD = 3.3V, VI = VDD or VSS fMAINCLK = 10MHz(MAX), Output = open VDD = 3.3V, IOCS, MCS = VDD Other VI = VDD or VSS fixed
IDD(S)
Notes 1: Normal input terminal --- A<14:0>, D<15:0> 2: Schmidt trigger input terminal --- All input pins except for A<14:0>, D<15:0>
STANDARD CHARACTERISTICS (Ta=25 C )
SUPPLY CURRENT VS OPERATING FREQUENCY (DISPLAY MODE 1) 50 VDD=5.5V VDD=3.3V 50 VDD=5.5V VDD=3.3V SUPPLY CURRENT VS OPERATING FREQUENCY (DISPLAY MODE 3)
40
40
30
30
20
20
10
10
0 2 4 6 8 10 12 14 16 OPERATING FREQUENCY f (MHz)
0 2 4 6 8 10 12 f (MHz) 14 16 OPERATING FREQUENCY
SUPPLY CURRENT VS OPERATING FREQUENCY (DISPLAY MODE 6) 50 VDD=5.5V VDD=3.3V 30
40
20
10
0 2 4 6 8 10 OPERATING FREQUENCY f 12 14 (MHz) 16
23
MITSUBISHI
M66273FP
Ver.3.1 Dec,1999
LCD CONTROLLER with VRAM
5V version support spcification SWITCHING CHARACTERISTICS (VDD=5V10%, Ta=-20~+75 C )
Symbol
ta(IOCS-D) ta(MCS-D) ta(RD-D) tdis(IOCS-D) tdis(MCS-D) tdis(RD-D) tpHL(MCS-WAIT) tpHL(WR-WAIT) tpHL(RD-WAIT) tpHL(WC-WAIT)
Parameter
IOCS data access time MCS data access time RD data access time Output disable time after IOCS Output disable time after MCS Output disable time after RD WAIT output propagation time after MCS WAIT output propagation time after WR WAIT output propagation time after RD WAIT output propagation time after WAITCNT
Test condition
Min.
Limits Ty p.
Max. 70 20
Unit ns ns
15 15 CL=50pF 30 30 30 30 30 30 30 0
ns ns ns ns ns ns ns ns ns ns
tpLH(CLK-WAIT) WAIT output propagation time after MPUCLK tpd(CLK-CP) tpLH(CLK-LP) tpHL(CLK-LP) ta(VD) tpLH(CLK-FLM) tpHL(CLK-FLM) tpd(CLK-M) tpLH(CLK-LE) tpHL(CLK-LE) tpLH(CLK-CSE) tpHL(CLK-CSE) tpd(D-WAIT)
CP output propagation time after MPUCLK LP output propagation time after MPUCLK VD access time FLM output propagation time after MPUCLK M output propagation time after MPUCLK LCDENB output propagation time after MPUCLK CSE output propagation time after MPUCLK Data definite time before cancelling WAIT
TIMING REQUIREMENTS (V DD=5V10%, Ta=-20~+75 C ) (1) Accessing to control register
Symbol tW(CS) tW(LWR) tsu(D-CS) tsu(D-LWR) th(CS-D) th(LWR-D) tsu(A-CS) tsu(A-LWR) tsu(A-RD) th(CS-A) th(LWR-A) th(RD-A) Parameter
IOCS/MCSpulse width LWR pulse width Data set up time before rising edge of IOCS/MCS Data set up time before rising edge of LWR Data hold time after rising edge of IOCS/MCS Data hold time after rising edge of LWR Address set up time before falling edge of IOCS/MCS Address set up time before falling edge of LWR Address set up time before falling edge of RD Address hold time after rising edge of IOCS/MCS Address hold time after rising edge of LWR Address hold time after rising edge of RD
Test condition
Min. 35 20 2 10
Limits Ty p.
Max.
Unit ns ns ns ns
0
ns
(2) Accessing to VRAM
Symbol tW(MCS) tW(WR) tsu(D-MCS) tsu(D-WR) th(MCS-D) th(WR-D) tsu(A-MCS) tsu(A-WR) tsu(A-RD) th(MCS-A) th(WR-A) th(RD-A) tsu(D-CLKD)
MCS pulse width WR pulse width Data set up time before rising edge of MCS Data set up time before rising edge of WR Data hold time after rising edge of MCS Data hold time after rising edge of WR Address set up time before falling edge of MCS Address set up time before falling edge of WR Address set up time before falling edge of RD Address hold time after rising edge of MCS Address hold time after rising edge of WR Address hold time after rising edge of RD Data set up time before rising edge of WAIT
Parameter
Test condition
Min. 35 20 2 10
Limits Ty p.
Max.
Unit ns ns ns ns ns ns ns
0 tsu(CLK)+10 5
tsu(MCS-WC) MCS set up time before falling edge of WAITCNT
24
* tc(CLK)=MPUCLK cycle time
MITSUBISHI
M66273FP
Ver.3.1 Dec,1999
LCD CONTROLLER with VRAM
(3) Clock and accessing to LCD display
Symbol tc(CLK) tWH(CLK) tWL(CLK) Parameter
MPUCLK cycle time MPUCLK "H" pulse width MPUCLK "L" pulse width Display mode 1,2,3,5,6
Test condition
Min.
50
Limits Ty p.
Max.
Unit ns
tC(CLK) 2 tC(CLK) (1/n) 2 * tC(CLK) (1/n) tC(CLK) 2 * (1/n)
ns
ns ns
tC(CP)
CP syscle time Display mode 4
tWH(CP) tWL(CP) tWH(CP) tWL(CP)
CP "H" pulse width Display mode 1,2,3,5,6 CP "L" pulse width CP "H" pulse width Display mode 4 CP "L" pulse width Display mode 1,2,3,5,6
ns
tC(CLK) (1/n) tC(CLK) * LPW (1/n) 2 * tC(CLK) * LPW (1/n)
ns
ns ns
tW(FLM)
FLM pluse width Display mode 4
Note : Clock frequency of MPUCLK input is less than fmax = 20MHz. Limit of clock for the internal operation is fmax = 15MHz. When MPUCLK is more than 15MHz from extemal input,set clock for the internal operation up to 15MHz by using division of DIV register. Division is set with rising dege of MPUCLK input.
1/n =Division of MPUCLK LPW =Setting value of LPW register
25
MITSUBISHI
M66273FP
Ver.3.1 Dec,1999
LCD CONTROLLER with VRAM
3V version support spcification SWITCHING CHARACTERISTICS (VDD=3V10%, Ta=-20~+75 C )
Symbol
ta(IOCS-D) ta(MCS-D) ta(RD-D)
Parameter
Test condition
Min.
Limits Ty p.
Max. 100 30 25 25
Unit ns ns ns ns ns ns ns ns ns ns ns ns
IOCS data access time MCS data access time RD data access time Output disable time after IOCS tdis(IOCS-D) Output disable time after MCS tdis(MCS-D) tdis(RD-D) Output disable time after RD tpHL(MCS-WAIT) WAIT output propagation time after MCS tpHL(WR-WAIT) WAIT output propagation time after WR tpHL(RD-WAIT) WAIT output propagation time after RD tpHL(WC-WAIT) WAIT output propagation time after WAITCNT
tpLH(CLK-WAIT) WAIT output propagation time after MPUCLK tpd(CLK-CP) tpLH(CLK-LP) tpHL(CLK-LP) ta(VD) tpLH(CLK-FLM) tpHL(CLK-FLM) tpd(CLK-M) tpLH(CLK-LE) tpHL(CLK-LE) tpLH(CLK-CSE) tpHL(CLK-CSE) tpd(D-WAIT)
CP output propagation time after MPUCLK LP output propagation time after MPUCLK VD access time FLM output propagation time after MPUCLK M output propagation time after MPUCLK LCDENB output propagation time after MPUCLK CSE output propagation time after MPUCLK Data definite time before cancelling WAIT
CL=50pF
40 40 40 40 40 40 40 0
TIMING REQUIREMENTS (VDD=3V10%, Ta=-20~+75 C ) (1) Accessing to control register
Symbol tW(CS) tW(LWR) tsu(D-CS) tsu(D-LWR) th(CS-D) th(LWR-D) tsu(A-CS) tsu(A-LWR) tsu(A-RD) th(CS-A) th(LWR-A) th(RD-A) Parameter
IOCS/MCS pulse width LWR pulse width Data set up time before rising edge of IOCS/MCS Data set up time before rising edge of LWR Data hold time after rising edge of IOCS/MCS Data hold time after rising edge of LWR Address set up time before falling edge of IOCS/MCS Address set up time before falling edge of LWR Address set up time before falling edge of RD Address hold time after rising edge of IOCS/MCS Address hold time after rising edge of LWR Address hold time after rising edge of RD
Test condition
Min. 50 30 2 15
Limits Ty p.
Max.
Unit ns ns ns ns
0
ns
(2) Accessing to VRAM
Symbol tW(MCS) tW(WR) tsu(D-MCS) tsu(D-WR) th(MCS-D) th(WR-D) tsu(A-MCS) tsu(A-WR) tsu(A-RD) th(MCS-A) th(WR-A) th(RD-A) tsu(D-CLK)
MCS pulse width WR pulse width Data set up time before rising edge of MCS Data set up time before rising edge of WR Data hold time after rising edge of MCS Data hold time after rising edge of WR Address set up time before falling edge of MCS Address set up time before falling edge of WR Address set up time before falling edge of RD Address hold time after rising edge of MCS Address hold time after rising edge of WR Address hold time after rising edge of RD Data set up time before rising edge of WAIT
Parameter
Test condition
Min. 50 30 2 15
Limits Ty p.
Max.
Unit ns ns ns ns ns ns ns
0 tc(CLK)+15 7
tsu(MCS-WC) MCS set up time before falling edge of WAITCNT
26
* tc(CLK)=MPUCLK cycle time
MITSUBISHI
M66273FP
Ver.3.1 Dec,1999
LCD CONTROLLER with VRAM
(3) Clock and accessing to LCD display
Symbol tc(CLK) tWH(CLK) tWL(CLK) Parameter
MPUCLK cycle time MPUCLK "H" pulse width MPUCLK "L" pulse width Display mode 1,2,3,5,6
Test condition
Min.
50
Limits Ty p.
Max.
Unit ns
tC(CLK) 2 tC(CLK) (1/n) 2 * tC(CLK) (1/n) tC(CLK) 2 * (1/n)
ns
ns ns
tC(CP)
CP syscle time Display mode 4
tWH(CP) tWL(CP) tWH(CP) tWL(CP)
CP "H" pulse width Display mode 1,2,3,5,6 CP "L" pulse width CP "H" pulse width Display mode 4 CP "L" pulse width Display mode 1,2,3,5,6
ns
tC(CLK) (1/n) tC(CLK) * LPW (1/n) 2 * tC(CLK) * LPW (1/n)
ns
ns ns
tW(FLM)
FLM pluse width Display mode 4
Note : Clock frequency of MPUCLK input is less than fmax = 20MHz. Limit of clock for the internal operation is fmax = 10MHz. When MPUCLK is more than 10MHz from extemal input,set clock for the internal operation up to 10MHz by using division of DIV register. Division is set with rising dege of MPUCLK input.
1/n =Division of MPUCLK LPW =Setting value of LPW register
Test circuit
Input VDD
VDD
RL=1KOhm SW1
Parameter
D<15:0>
SW2
tdis(LZ) tdis(HZ) ta(ZL) ta(ZH)
SW1 Closed Open Closed Open
SW2 Open Closed Open Closed
P.G
50Ohm
DUT
CL RL=1KOhm
VSS
CL
Outputs except for D<15:0>
(1) Input pulse level: 0 to 3V Input pulse rise/fall time: tr,tf=3ns Input decision voltage: 1.5V Output decision voltage: VDD/2 (However,tdis(LZ) is 10% of output amplitude and tdis(HZ) is 90% of that for dezision.) (2) Load capacity CL include float capacity of connection and input capacity of probe.
27
MITSUBISHI
M66273FP
Ver.3.1 Dec,1999
LCD CONTROLLER with VRAM
TIMING DIAGRAM (1) Write to control register ( RD = "H") No WAIT
tw(CS)
IOCS (or MCS)
tw(LWR)
LWR
"H"
WAIT
tsu(D-CS) tsu(D-LWR) th(CS-D) th(LWR-D)
Note 1
D<7:0>
tsu(A-CS) tsu(A-LWR)
Data input is established
th(CS-A) th(LWR-A)
A<7:0> (or A<14:0>)
Address is established
(2) Read from control register (LWR= "H") No WAIT
IOCS (or MCS) RD
"H"
WAIT
ta(CS-D) ta(RD-D) tdis(CS-D) tdis(RD-D)
Note 1
D<7:0>
tsu(A-CS) tsu(A-RD)
Data output is established
th(CS-A) th(RD-A)
A<7:0> (orA<14:0>)
Address is established
Note 1 : D<15:0> is used only when 16bit MPU controls the LCD module built-in type support function. 2 : Writing/reading operation for the control register is performed during "L" overlapping of IOCS or MCS and LWR or RD input signal. Limits of IOCS,MCS, LWR and RD are prescribed by the input signal of last change to "L" in starting access, and by the input signal of first change to "H" in ending access.
28
MITSUBISHI
M66273FP
Ver.3.1 Dec,1999
LCD CONTROLLER with VRAM
(3) Write to VRAM
( RD = "H" )
Term of non cycle steal access
tw(MCS)
MCS
tw(WR)
LWR (+HWR) WAIT
tsu(D-MCS) tsu(D-WR) th(MCS-D) th(WR-D)
"H"
D<7:0> (D<15:0>)
Data input is established
tsu(A-MCS) tsu(A-WR) th(MCS-A) th(WR-A)
A<14:0> (+BHE)
Address is established
(4) Read from VRAM
(LWR, HWR = "H")
Term of non cycle steal access
MCS
RD
WAIT
ta(MCS-D) ta(RD-D) tdis(MCS-D) tdis(RD-D)
"H"
D<7:0> (D<15:0>)
Data output is established
tsu(A-MCS) tsu(A-RD) th(MCS-A) th(RD-A)
A<14:0>
Address is established
Note 3 : Writing/reading operation for VRAM during non cycle steal access is performed during "L" overlapping of MCS and LWR (+HWR) or RD input signal. Limits of MCS, LWR (+HWR) and RD are prescribed by the input signal of last change to "L" in starting access, and by the input signal of first change to "H" in ending access.
29
MITSUBISHI
M66273FP
Ver.3.1 Dec,1999
LCD CONTROLLER with VRAM
(5) Write to VRAM ( RD = "H",WAITCNT= "L" or "H" fixed ) Term of cycle steal access (and When setting register WAITC to "0")
tC(CLK) tWH(CLK) tWL(CLK)
MPUCLK
tw(MCS)
MCS
tw(WR)
LWR (+HWR) WAIT
tpHL(MCS-WAIT) tpLH(CLK-WAIT)
tpHL(WR-WAIT)
tsu(D-CLK)
th(MCS-D) th(WR-D)
D<7:0> (D<15:0>)
Data input is established
tsu(A-MCS) tsu(A-WR) th(MCS-A) th(WR-A)
A<14:0> (+BHE)
Address is established
(6) Read from VRAM( LWR, HWR = "H",WAITCNT = "L" or "H" fiexed) Term of cycle steal access (and when setting segester WAITC to "0")
tC(CLK) tWH(CLK) tWL(CLK)
MPUCLK
MCS
RD
WAIT
tpHL(MCS-WAIT) tpHL(RD-WAIT) ta(MCS-D) ta(RD-D)
tpLH(CLK-WAIT)
tdis(MCS-D) tpd(D-WAIT) tdis(RD-D)
D<7:0> (D<15:0>)
Data output is established
tsu(A-MCS) tsu(A-RD) th(MCS-A) th(RD-A)
A<14:0>
Address is established
Note 4 :Writing/reading operation for VRAM during cycle steal access needs 0.5tc(MAINCLK) + 1tc(CLK) in best case or 2.5tc(MAINCLK)+1tc(CLK) in worst case, according to the condition of the internal cycle steal at starting access requested from MPU. Data output D is established before changing WAIT output. tc(MAINCLK ) = Reference clock cycle time for internal operation after setting division of MPUCLK. 5 : Limits of MCS, LWR (+HWR) and RD are prescribed by the input signal of last change to "L" in starting access, and by the input signal of first change to "H" in ending access. 6 : Always once return MCS, LWR (+HWR) or RD to "H" after canceling WAIT output. In case of latching "L", as next WAIT does not output, this causes malfunction to occur. 30
MITSUBISHI
M66273FP
Ver.3.1 Dec,1999
LCD CONTROLLER with VRAM
(7) Write to VRAM ( RD = "H" ) Term of cycle steal access (and When setting register WAITC to "1")
tC(CLK) tWH(CLK) tWL(CLK)
MPUCLK
tw(MCS)
MCS WAITCNT
tsu(MCS-WC)
LWR (+HWR) WAIT
tpHL(WC-WAIT) tpLH(CLK-WAIT) th(MCS-D) tsu(D-CLK) th(WR-D)
D<7:0> (D<15:0>)
tsu(A-WR)
Data input is established
th(MCS-A) th(WR-A)
A<14:0> (+BHE)
Address is established
(8) Read from VRAM ( LWR, HWR = "H") Term of cycle steal access (and when setting register WAITC to "1")
tC(CLK) tWH(CLK) tWL(CLK)
MPUCLK
MCS
WAITCNT
tsu(MCS-WC)
RD
WAIT
tpHL(WC-WAIT)
tpLH(CLK-WAIT) tdis(MCS-D) ta(RD-D) tpd(D-WAIT) tdis(RD-D)
D<7:0> (D<15:0>)
tsu(A-RD)
Data output is established
th(MCS-A) th(RD-A)
A<14:0>
Address is established
Note 7 : Writing/reading operation for VRAM during cycle steal access needs 0.5tc(MAINCLK) + 1tc(CLK) in best case or 2.5tc(MAINCLK)+1tc(CLK) in worst case, according to the condition of the internal cycle steal at starting access requested from MPU. Data output D is established before changing WAIT output. tc(MAINCLK ) = Reference clock cycle time for internal operation after setting division of MPUCLK. 8 : When setting WAITC to "1" , MCS is necessary to change "L" earier than LWR (+HWR) ,RD. Limits of MCS, LWR (+HWR) and RD are prescribed by the input signal of last change to "L" in starting access, and by the input signal of first change to "H" in ending access. 9 : Always once return MCS, LWR (+HWR) or RD to "H" after canceling WAIT output. In case of latching "L", as next WAIT does not output, this causes malfunction to occur. 31
MITSUBISHI
M66273FP
Ver.3.1 Dec,1999
LCD CONTROLLER with VRAM
(9) Interface timing with LCD (DIV = 1 division : set ) (9-1) LCD display data transfer
* When DIV = 1 division, MAINCLK for internal operation = MPUCLK input.
tC(CLK) tWH(CLK) tWL(CLK)
MPUCLK
tpd(CLK-CP) tC(CP) tWL(CP) tWH(CP)
CP
tpLH(CLK-LP) tpHL(CLK-LP)
LP
ta(VD)
VD
Data is indefinite
(9-2) Control signal
MPUCLK CP LP
tpLH(CLK-FLM)
tpHL(CLK-FLM)
FLM
tW(FLM) tpd(CLK-M)
M
tpLH(CLK-LE) tpHL(CLK-LE)
LCDENB
Note 10 :
Output signal to LCD side is synchronized with MAINCLK (reference clock for internal operation). When division is set to 1/2 to 1/16 by DIV register, switching characteristics is defined by rising edge of MPUCLK.
(10) CSE output timing (DIV=1 divison : set)
MPUCLK
tpHL(CLK-CSE) tpLH(CLK-CSE)
CSE
32
MITSUBISHI
M66273FP
Ver.3.1 Dec,1999
LCD CONTROLLER with VRAM
FLOWCHART
EXAMPLE OF INITIALIZE ON DISPLAY MODE 3 (STANDARD ACCESS)
Start
Example of setting
Note ) When use software reset, surely return to reset off after reset on. And then, can't set another bits (D6 to D0) at the same time.
System reset RESET input ="L" or use R1-D7(RESET)bit
#
R1:Basic operation mode register (RESET,IDXON,DIV,DISP,REV,LCDE)
(00H)
Set IDXON=OFF,DISP=OFF. (Set RESET,IDXON,DIV when register is initialized.) Set display mode, only when register is initialized.
R2:MPU/LCD mode register (WAITC,SWAP,DUAL,GRAY,4/8)
(02H) (50H) (04H) (04H) (78H) (00H) (00H) (07H)
Note ) Set R1-D6(IDXON) and R2 register at the beginning of initializing register after system reset.
R3:Number of horizontal display characters register(CR) R4:Horizontal synchronous pulse width register(LPW)
R5:Cycle steal enable width register(CSW)
Set suitable value for LCD. (Set these value only when register is initialized.)
R6:Number of vertical lines register(SLT)
#
R7:1st screen display start address register(SA1L) R8:2nd screen display start address register(SA1H) R11:M output frequency variable register(MT)
Set lower address of 1st screen display start address. Set upper address of 1st screen display start address. Set suitable value for LCD. (Set MT only when register is initialized.) Set gray scale pattern. Note ) When access to R17 to R80, must be set DISP=OFF. Can't access to R17 to R80 on DISP=ON.
#
R17 to R80:Gray scale pattern register
Write display data to VRAM
Set display data to VRAM.
N
Complete?
Y
#
R1:Basic operation mode register (RESET,IDXON,DIV,DISP,REV,LCDE)
(05H)
Set DISP=ON.
Display start
Setting example suppose LCD size = 320x240dots and display mode 3 (Single scan,Gray scale, 4bit transfer). # Can change R1(DISP,REV,LCDE),R7(SA1L),R6(SA1h) registers value during display on.
33
MITSUBISHI
M66273FP
Ver.3.1 Dec,1999
LCD CONTROLLER with VRAM
EXAMPLE OF INITIALIZE ON DISPLAY MODE 3 (LCD MODULE BUILT-IN ACCESS) Example of setting
Note ) When use software reset, surely return to reset off after reset on. And then, can't set another bits (D6 to D0) at the same time.
Start
System reset RESET input ="L" or use R1-D7(RESET)bit
#
R1:Basic operation mode register (RESET,IDXON,DIV,DISP,REV,LCDE)
(40H)
Set IDXON=ON,DISP=OFF. (Set RESET,IDXON,DIV when register is initialized.) Set display mode, only when register is initialized.
R2:MPU/LCD MODE REGISTER (WAITC,SWAP,DUAL,GRAY,4/8)
(02H) Note ) Set R1-D6(IDXON) and R2 register at the beginning
of initializing register after system reset.
R3:Number of horizontal display characters register(CR) R4:Horizontal synchronous pulse width register(LPW)
(50H) (04H) (04H) (78H) (00H) (00H) (07H)
Set lower address of 1st screen display start address.
Set suitable value for LCD. (Set these value only when register is initialized.)
R5:Cycle steal enable width register(CSW)
R6:Number of vertical lines register(SLT)
# #
R7:1st screen display start address register(SA1L)
R8:2nd screen display start address register(SA1H)
Set upper address of 1st screen display start address. Set suitable value for LCD. (Set MT only when register is initialized.) Set gray scale pattern.
R11:M output frequency variable register(MT)
R17 to R80:Gray scale patternregister Discontinuous address R12,R13 or R15:VRAM address indexregister Continuous address
Note ) When access to R17 to R80, must be set DISP=OFF. Can't access to R17 to R80 on DISP=ON.
Set display data to VRAM.
R14 or R16:Data port register
N
Complete?
Y
#
R1:Basic operation mode register (RESET,IDXON,DIV,DISP,REV,LCDE)
(45H)
Set DISP=ON.
Display start
Setting example suppose LCD size = 320x240dots and display mode 3 (Single scan,Gray scale, 4bit transfer). # Can change R1(DISP,REV,LCDE),R7(SA1L),R6(SA1h) registers value during display on.
34

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